Personal computers (PC's) and other hosts store large amounts of data in mass-storage devices such as hard disk drives (HDD). Mass-storage devices are block-addressable rather than byte-addressable, since the smallest unit that can be read or written is a page that is several 512-byte sectors in size. Flash memory is replacing hard disks and optical disks as the preferred mass-storage medium.
NAND flash memory is a type of flash memory constructed from electrically-erasable programmable read-only memory (EEPROM) cells, which have floating gate transistors. These cells use quantum-mechanical tunnel injection for writing and tunnel release for erasing. NAND flash is non-volatile so it is ideal for portable devices storing data. NAND flash tends to be denser and less expensive than NOR flash memory.
However, NAND flash has limitations. In the flash memory cells, the data is stored in binary terms—as ones (1) and zeros (0). One limitation of NAND flash is that when storing data (writing to flash), the flash can only write from ones (1) to zeros (0). When writing from zeros (0) to ones (1), the flash needs to be erased a “block” at a time. Although the smallest unit for read or program can be a byte or a word, the smallest unit for erase is a block.
Single Level Cell (SLC) flash and Multi Level Cell (MLC) flash are two types of NAND flash. The erase block size of SLC flash may be 128K+4K bytes while the erase block size of MLC flash may be 256K+8K bytes. Another limitation is that NAND flash memory has a finite number of erase cycles between 10,000 to 1,000,000, after which the flash wear out and becomes unreliable.
Comparing MLC flash with SLC flash, MLC flash memory has advantages and disadvantages in consumer applications. In the cell technology, SLC flash stores a single bit of data per cell, whereas MLC flash stores two or more bits of data per cell. MLC flash can have twice or more the density of SLC flash with the same technology. But the performance, reliability and durability may decrease for MLC flash.
A consumer may desire a large capacity flash-memory system, perhaps as a replacement for a hard disk. A solid-state disk (SSD) made from flash-memory chips has no moving parts and is thus more reliable than a rotating disk.
Several smaller flash drives could be connected together, such as by plugging many flash drives into a USB hub that is connected to one USB port on a host, but then these flash drives appear as separate drives to the host. For example, the host's operating system may assign each flash drive its own drive letter (D:, E:, F:, etc.) rather than aggregate them together as one logical drive, with one drive letter. A similar problem could occur with other bus protocols, such as Serial AT-Attachment (SATA), integrated device electronics (IDE), and Peripheral Components Interconnect Express (PCIe). The parent application, now U.S. Pat. No. 7,103,684, describes a single-chip controller that connects to several flash-memory mass-storage blocks.
Larger flash systems may use several channels to allow parallel access, improving performance. A wear-leveling algorithm allows the memory controller to remap logical addresses to different physical addresses so that data writes can be evenly distributed. Thus the wear-leveling algorithm extends the endurance of the MLC flash memory.
What is desired is a multi-channel flash system with single-chip flash-memory devices in each of the channels. A smart storage switch or hub is desired between the host and the multiple single-chip flash-memory devices so that the multiple channels of flash are aggregated together into a single logical drive. It is further desired that the smart storage switch interleaves and stripes data accesses to the multiple channels of single-chip flash-memory devices, and that each of the single-chip flash-memory devices may further perform internal interleaving, wear-leveling, and address remapping.